Even when you just want to simulate, you still need a checkpoint file (we recommend the one for the FlashGT card). This file contains a snapshot at a certain build step and has to be integrated when building your action. The PSL will be part of the circuit on the FPGA and is synthesised and layouted for your specific FPGA, provided as a Vivado checkpoint (.dcp) file. If you do not want to repeat this after every reboot, do it automatically on startup by appending it to your bashrc: ~ $ echo "source /opt/Xilinx/Vivado/2016.4/settings64.sh" > ~/.bashrc Add Vivado to your path by sourcing its settings file: ~ $ source /opt/Xilinx/Vivado/2016.4/settings64.sh.If not using the evaluation version, obtain a Vivado license-file (.lic).The free 30-day evaluation should work as well ( Comparison of different Vivado Editions). As the HL WebPACK Edition may not include support for your FPGA-chip we recommend the HL Design Edition. Currently version 2016.4 is the latest supported release of Vivado. Xilinx Vivado is used to synthesize and layout our actions for the FPGA and contains HLS to convert C++ to hardware code as well as xsim (Vivado Simulator) for simulating without an FPGA.
Vivado download 2016.4 install#
Let's first download, install and configure the software and repositories we need on our development machine.
In our setup we used Ubuntu 16.04, but although not officially supported by the needed Vivado version, working with Ubuntu 17.04 should also be possible. In order to work with SNAP and CAPI, the most important requirement is to install Xilinx Vivado.
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